An unclamped inductive switching (UIS) test implemented by known test systems can be destructive to a device under test (DUT), devices near the device under test, and/or test equipment (e.g., test probes, test boards, test circuitry) associated with the device under test in the event that the device under test fails (e.g., fails catastrophically). In other words, using known test systems a device under test that fails a UIS test implemented by known test systems can be destroyed and/or can cause damage to adjacent (e.g., surrounding, relatively close proximity) devices and/or test equipment. Collateral damage caused to adjacent devices can, for example, result in lower wafer sort yields, and failing UIS events can result in transient power surges to test equipment when the device under test is shorted from, for example, electrical overstress. In addition, hardware limitations for known test systems can result in test conditions at wafer sort test (e.g., test currents at wafer sort) that can be mismatched with those used in package level testing and/or field use. This mismatch can result in unreliable devices being needlessly built into packages at a relatively large cost because the devices could not be effectively screened at wafer sort test. Thus, a need exists for systems, methods, and apparatus to address the shortfalls of present technology and to provide other new and innovative features.